/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-01/vhdl-2021-07-16/FullAdder.vhdl

entity HalfAdder is
port
(
    a: in bit;
    b: in bit;
    s: out bit;
    c: out bit
);
end;

entity FullAdder is
port
(
    x: in bit;
    y: in bit;
    cin: in bit;
    sout: out bit;
    cout: out bit   
);
end;

architecture structural of HalfAdder is
    signal at, bt, st, ct: bit;
begin
    at <= a;
    bt <= a;
    st <= at xor bt;
    ct <= at and bt;
    s <= st;
    c <= ct;
end structural;

architecture structural of FullAdder is
    signal s1, s2, s3, s4, s5, s6, s7 : bit;
    component HalfAdder 
    port 
    (
            x: in bit;
            y: in bit;
            s: out bit;
            c: out bit
    );
    end component;
begin     
    u1 : HalfAdder PORT MAP (x, y, s1, s2);
    u2 : HalfAdder PORT MAP (s1, cin, sout, s3);
    cout <= s5 or s7;
end structural;