.CSEG
.DSEG
.ORG
.DB
.DW
.BYTE
lds direkt
ldd indiziert
ld indirekt
sts direkt
std indiziert
st indirekt
X-Pointer: r26, r27
Y-Pointer: r28, r29
Z-Pointer: r30, r31
Carry-Flag: c
Negativ-Flag: n
Sign-Flag: s
Zero-Flag: z
Zweier-Komplement-Überlauf-Flag: v
Transfer Enable Flag: t
Global Interrupt Enable Flag: i
brbs
brbc
brts
brtc
brvs
brvc
brie
brid
brlo
brpl
brsh
brmi
...
sec
sen
ses
sez
sev
set
sei
clc
cln
cls
clz
clv
clt
cli
add
adc
adiw
inc
sub
subi
sbc
dec
lsl
lsr
rol
ror
asr
swap
st X, r0
st X+, r0
st -X, r0
ldd r0, Y+k
std Y+k, r0
bswap
cbw
cdq
cwde
cwd
pusha
popa
pushad
popad
pushw
popaw
xlat
jo
jno
jp
jnp
jpe
jpo
js
jns
jcxz
jecxz
VCC, GND
CLK
S2, S1, S0
CEN
DEN
ANE
ALE
IOB
IOWC
IORC
DT/R
MWTC
MRDC
IOWC
...
Xilinx
Altera
Lattice
Cyprex
Actel
Atmel
PLA: Programmable Logic Array
PAL: Programmable Array Logic
PLD: Programmable Logic Device
CPLD: Complex Programmable Logic Device
FPGA: Field Programming Gate Array
PLA: Programmierbare UND-Matrix, programmierbare ODER-Matrix
PAL: ODER-Matrix fest verdrahtet
PROM: Programmierbare ODER-Matrix
Virtex 5, 7
Coolrunner
Xintex
public phys_clicks alloc_mem (phys_clicks clicks) {
register struct hole *hp, *prev_ptr;
phys_clicks old_base;
hp = hole;
while (hp != NIL_HOLE) {
if (hp->h_len >= clicks) {
old_base = hp->h_base;
hp->h_base += clicks;
hp->h_len -= clicks;
if (hp->h_len != 0)
return old_base;
del_slot (prev_ptr, hp);
return old_base;
}
prev_ptr = hp;
hp = hp->h_next;
}
return E_NO_MEM;
}
mm/glo.h
mm/const.h
mm/mproc.h
mm/param.h
mm/alloc.c
mm/break.c
mm/forkexit.c
mm/exec.c
mm/table.c
mm/putc.c
mm/getset.c
mm/signal.c
alloc_mem ()
free_mem ()
del_slot ()
merge ()
max_hole ()
mem_init ()
