/media/sda-magnetic/david/Dok-15-2023-11-27/Dokumente-15-appended-2023-10-11/append-temporarly/rslatch.vhdl

Jetzt schreiben wir ein RS-Latch in VHDL

[code]
entity RS_LATCH is
port
(
    r: in bit;
    s: in bit;
    q1: inout bit;
    q2: inout bit
);
end;

architecture behaviour of RS_LATCH is
begin
    q1 <= (r nor q2);
    q2 <= (s nor q1);
end;
[/code]