lcd hd44780

;; (c) david vajda
;; 07/22/2026
;; lcd44780

.include "m8def.inc"

ldi r16, HIGH (RAMEND)
out SPH, r16
ldi r16, LOW (RAMEND)
out SPL, r16
ldi r16, 0xff
out DDRB, r16

rcall hd44780init001

main001:
ldi ZH, HIGH (2*msg)
ldi ZL, LOW (2*msg)
hd44780mainloop001:
lpm r16, Z+
cpi r16, 0x00
breq hd44780mainloop001
rcall hd44780putc001
rcall waitingloop1s001
rjmp main001

msg: .db "david@https://www.vajda-breadboard.de", 10, 13, 0

hd44780init001:
ldi r16, 50
hd44780init001loop001:
rcall hd44780waitlooplong001
dec r16
brne hd44780init001loop001
ldi r16, 0x03
rcall hd44780waitlooplong001
ldi r16, 0x03
rcall hd44780waitloopshort001
ldi r16, 0x03

ldi r16, 0x02
out PORTB, r16
rcall hd44780enable001
rcall hd44780waitlooplong001

ldi r16, 0x20
rcall hd44780cmd001
rcall hd44780enable001
rcall hd44780waitlooplong001
ret

hd44780waitlooplong001:
push r16
push r17
ldi r16, 0x21
hd44780waitlooplong001l001:
ldi r17, 0xC9
hd44780waitlooplong001l002:
dec r17
breq hd44780waitlooplong001l002
dec r16
breq hd44780waitlooplong001l001
pop r17
pop r16
ret

hd44780waitloopshort001:
push r16
ldi r16, 42
hd44780waitloopshort001l001:
dec r16
breq hd44780waitloopshort001l001
pop r16
ret

hd44780enable001:
sbi PORTB, 5
nop
nop
nop
cbi PORTB, 5
ret

hd44780putc001:
mov r17, r16
swap r16
andi r16, 0x0f
out PORTB, r16
rcall hd44780enable001
andi r17, 0x0f
out PORTB, r17
rcall hd44780enable001
ret

hd44780cmd001:
mov r17, r16
swap r16
andi r16, 0x0f
ori r16, 0b00010000
out PORTB, r16
rcall hd44780enable001
andi r17, 0x0f
ori r17, 0b00010000
out PORTB, r17
rcall hd44780enable001

ret

waitingloop1s001:
push r16
push r17
push r18
ldi r18, 0x04
waitingloop1sl001:
ldi r17, 0xff
waitingloop1sl002:
ldi r16, 0xff
waitingloop1sl003:
dec r16
breq waitingloop1sl003
dec r17
breq waitingloop1sl002
dec r18
breq waitingloop1sl003
pop r18
pop r17
pop r16
ret

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