/media/sda-magnetic/david/Extern-Magnetic-2022-06-29/Extern01/Dokumente-11-2021-07-05/informatik-math/vhdl-2021-07-16/HalfAdder.vhdl

entity HalfAdder is
port
(
    a: in bit;
    b: in bit;
    s: out bit;
    c: out bit
);
end;

architecture structural of HalfAdder is
    signal at, bt, st, ct: bit;
begin
    at <= a;
    bt <= a;
    st <= at xor bt;
    ct <= at and bt;
    s <= st;
    c <= ct;
end structural;