entity HalfAdder is
port
(
a: in bit;
b: in bit;
s: out bit;
c: out bit
);
end;
entity FullAdder is
port
(
x: in bit;
y: in bit;
cin: in bit;
sout: out bit;
cout: out bit
);
end;
architecture structural of HalfAdder is
signal at, bt, st, ct: bit;
begin
at <= a;
bt <= a;
st <= at xor bt;
ct <= at and bt;
s <= st;
c <= ct;
end structural;
architecture structural of FullAdder is
signal s1, s2, s3, s4, s5, s6, s7 : bit;
component HalfAdder
port
(
a: in bit;
b: in bit;
so: out bit;
co: out bit
);
end component;
begin
s1 <= x;
s2 <= y;
s3 <= cin;
u1 : HalfAdder PORT MAP (s1, s2, s4, s5);
u2 : HalfAdder PORT MAP (s1, cin, s6, s7);
cout <= s5 or s7;
end structural;
