mov lea xchg add adc sub sbb mul div dec inc neg and or xor not lods lodsb lodsw lodsd stos stosb stosw stosd movs movsb movsw movsd rep jmp cmp call ret loop int iret je jne jg jng jge jnge jl jnl jle jnle ja jna jae jnae jb jnb jbe jnbe jz jnz jc jnc in out push pop bswap xlat cbw cdq cwd cwde pusha popa pushad popad pushaw popaw jcxz jecxz jo jno js jns jp jnp jpe jpo Sockel 423 Sockel 478 Sockel 775 1156 1155 1151 1150 1200 Westmere (Clarkdale) Sandy Bridge Ivy Bridge Haswell-DT Skylake-S Kaby Lake-S Coffee Lake-S Comet Lake-S Intel-Core-i3-530 Intel-Core-i3-540 Intel-Core-i3-550 Intel-Core-i3-560 Intel-Core-i3-21xx Intel-Core-i3-32xx Intel-Core-i3-41xx Intel-Core-i3-43xx Intel-Core-i3-60xx Intel-Core-i3-61xx Intel-Core-i3-63xx Intel-Core-i3-71xx Intel-Core-i3-73xx Intel-Core-i3-81xx Intel-Core-i3-83xx Intel-Core-i3-91xx Intel-Core-i3-93xx Intel-Core-i3-101xx Intel-Core-i3-103xx DDR-200 PC-1600 DDR-266 PC-2100 DDR-333 PC-2700 DDR-400 PC-3200 DDR2-... PC2-... DDR3-... PC3-... DDR4-... PC4-... DDR5-... PC5-... 8020 8021 8022 8035 8039 8040 8048 8049 8050 8648 8748 8749 8031 8032 8051 8052 8751 8752 add addc anl orl xrl inc dec clr cpl da swap rl rlc rr rrc mov lds ld ldd sts st std in out push pop lmp lds: direkt ld: indirekt ldd: indiziert sts: direkt st: indirekt std: indiziert st Y, r20 st Y+, r20 st -Y, r20 ld r20, Y ld r20, Y+ ld r20, -Y sts Y+5, r20 lds r20, Y+5 .CSEG .DSEG .ORG .DB .DW X-Pointer: r26, r27 Y-Pointer: r28, r29 Z-Pointer: r30, r31 Carry-Flag: c Negative-Flag: n Vorzeichen-Flag: s Zero-Flag: z Halbübertrag-Flag: h Zweierkomplement-Überlauf-Flag: v Transfer-Flag: t Globale Interrupt Enable Flag: i CLC CLN CLS CLZ CLH CLV CLT CLI SEC SEN SES SEZ SEH SEV SET SEI breq brne brge brsh brmi brpl brlo brlt brbs brbc brcs brcc brts brtc brvs brvc brhs brhc brid brie IRQ Interrupt-Request ISR Interrupt-Service-Routine Interrupt-Handler PIC 8259 A - Programmable Interrupt Controller 8259 A Eingänge: 8 Eingänge, IR0 .. IR7, an jedem Eingang hängt ein Gerät IR0 höchste Priorität, IR7 niedrigste INT angeschlossen an INTR der CPU INTA von CPU und Controller verbunden D7 .. D0, mit den acht niederwertigsten Leiterbahnen des Datenbusses verbunden VCC, GND D7 .. D0 A0 CAS2, CAS1, CAS0 IR7 .. IR0 INT -INTA -CS -WR -RD -SP/-EN IRQ 0 Timer IRQ 1 Keyboard IRQ 2 PIC 2 (Slave) IRQ 3 COM 1 IRQ 4 COM 2 IRQ 5 Soundcard IRQ 6 Floppy IRQ 7 Parallel/Harddisk PIT 8253 - Programmable Intervall Timer VCC, GND D7 .. D0 A1, A0 CLK2, OUT2, GATE2 CLK1, OUT1, GATE1 CLK0, OUT0, GATE0 -CS -WR -RD 8288 VCC, GND CLK S2, S1, S0: Status Input AEN: Address Enable CEN: Command Enable DEN: Data Enable ALE: Address Latch Enable IOB: Input Output Bus Mode IOWC: Input Output Write Command IORC: Input Output Read Command AIOWC: Advanced IO Write Command MWTC: Memory Write Command MRDC: Memory Read Command AMWC: Advanced Memory Write Command DT/R: Data Transmit/Recieve MCE/PDEN -INTA 8212 Ein- und Ausgabebaustein 8216 Treiber 8224 Oszillator 8226 Treiber 8228 Bus-Controller 8271 Floppy-Disk 8273 HDLC/SDLC 8278 Keyboard 8292 IEC 8294 Datenverschlüsselung 8295 Punkt-Matrix-Drucker 8282 Latch 8283 Latch 8284 Oszillator 8286 Treiber 8287 Treiber 8288 Bus-Controller 8289 Bus-Arbiter MCE2VGA GBS8219 GBS8200 HD44780 VSS VDD VEE RS RW E DB0 .. DB7 A K 1 Masse 2 Masse 3 4 5 6 Intensität 7 Video-Signal 8 H-Sync 9 V-Sync 1 Masse 2 Masse 3 R 4 G 5 B 6 Intensität 7 8 H-Sync 9 V-Sync