0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
8 1 0 0 0 1
9 1 0 0 1 1
11 1 0 1 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 1:
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
5 0 1 0 1 1
6 0 1 1 0 1
9 1 0 0 1 1
Gruppe 3:
11 1 0 1 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
4:5 0 1 0 -
4:6 0 1 - 0
8:9 1 0 0 -
6:14 - 1 1 0
9:11 1 0 - 1
11:15 1 - 1 1
14:15 1 1 1 -
6:14 - 1 1 0
11:15 1 - 1 1
4:6 0 1 - 0
9:11 1 0 - 1
4:5 0 1 0 -
8:9 1 0 0 -
14:15 1 1 1 -
Gruppe 2:
6:14 - 1 1 0
Gruppe 3:
11:15 1 - 1 1
Gruppe 1:
4:6 0 1 - 0
Gruppe 2:
9:11 1 0 - 1
Gruppe 1:
4:5 0 1 0 -
8:9 1 0 0 -
Gruppe 3:
14:15 1 1 1 -
6:14 - 1 1 0
11:15 1 - 1 1
4:6 0 1 - 0
9:11 1 0 - 1
4:5 0 1 0 -
8:9 1 0 0 -
14:15 1 1 1 -
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 1 4
5 0 1 0 1 1 5
6 0 1 1 0 1 6
7 0 1 1 1 0
8 1 0 0 0 1 8
9 1 0 0 1 1 9
10 1 0 1 0 0
11 1 0 1 1 1 11
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1 14
15 1 1 1 1 1 15
4 5 6 8 9 11 14 15
6:14 * *
11:15 * *
4:6 * *
9:11 * *
4:5 * *
8:9 * *
14:15 * *
4 5 6 8 9 11 14 15
6:14 * *
11:15 * *
4:6 * *
9:11 * *
4:5 * * p
8:9 * * p
14:15 * *
4 5 6 8 9 11 14 15
6:14 * *
11:15 * *
4:5 * * p
8:9 * * p
6:14 - 1 1 0
11:15 1 - 1 1
4:5 0 1 0 -
8:9 1 0 0 -
y <= (x2 and x1 and not x0) or
(x3 and x1 and x0) or
(not x3 and x2 and not x1) or
(x3 and not x2 and not x1);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240527 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240527 is
begin
y <= (x2 and x1 and not x0) or
(x3 and x1 and x0) or
(not x3 and x2 and not x1) or
(x3 and not x2 and not x1);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240527all is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240527all is
component quine20240527
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240527 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
