0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
1 0 0 0 1 1
3 0 0 1 1 1
6 0 1 1 0 1
7 0 1 1 1 1
10 1 0 1 0 1
11 1 0 1 1 1
13 1 1 0 1 1
Gruppe 1:
1 0 0 0 1 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
10 1 0 1 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
13 1 1 0 1 1
1:3 0 0 - 1
3:7 0 - 1 1
3:11 - 0 1 1
6:7 0 1 1 -
10:11 1 0 1 -
13 1 1 0 1
6:7 0 1 1 -
10:11 1 0 1 -
1:3 0 0 - 1
3:7 0 - 1 1
3:11 - 0 1 1
13 1 1 0 1
0 0 0 0 0 0
1 0 0 0 1 1 1
2 0 0 1 0 0
3 0 0 1 1 1 3
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1 6
7 0 1 1 1 1 7
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1 10
11 1 0 1 1 1 11
12 1 1 0 0 0
13 1 1 0 1 1 13
14 1 1 1 0 0
15 1 1 1 1 0
1 3 6 7 10 11 13
6:7 * *
10:11 * *
1:3 * *
3:7 * *
3:11 * *
13 *
1 3 6 7 10 11 13
6:7 * * p
10:11 * * p
1:3 * *
3:7 * *
3:11 * *
13 * p
1 3 6 7 10 11 13
6:7 * * p
10:11 * * p
1:3 * *
13 * p
6:7 0 1 1 -
10:11 1 0 1 -
1:3 0 0 - 1
13 1 1 0 1
y <= (not x3 and x2 and x1) or
(x3 and not x2 and x1) or
(not x3 and not x2 and x0) or
(x3 and x2 and not x1 and x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240521 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240521 is
begin
y <= (not x3 and x2 and x1) or
(x3 and not x2 and x1) or
(not x3 and not x2 and x0) or
(x3 and x2 and not x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240521testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240521testbench is
component quine20240521
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240521 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
