0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
12 1 1 0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 1:
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
3 0 0 1 1 1
9 1 0 0 1 1
12 1 1 0 0 1
Gruppe 3:
7 0 1 1 1 1
13 1 1 0 1 1
14 1 1 1 0 1
2:3 0 0 1 -
4:12 - 1 0 0
8:9 1 0 0 -
8:12 1 - 0 0
3:7 0 - 1 1
9:13 1 - 0 1
12:14 1 1 - 0
2:3 0 0 1 -
8:9 1 0 0 -
12:14 1 1 - 0
8:12 1 - 0 0
3:7 0 - 1 1
9:13 1 - 0 1
4:12 - 1 0 0
Gruppe 1:
2:3 0 0 1 -
8:9 1 0 0 -
Gruppe 2:
12:14 1 1 - 0
Gruppe 1:
8:12 1 - 0 0
Gruppe 2:
9:13 1 - 0 1
3:7 0 - 1 1
Gruppe 1:
4:12 - 1 0 0
Gruppe 1:
2:3 0 0 1 -
8:9 1 0 0 -
Gruppe 2:
12:14 1 1 - 0
Gruppe 1:
8:12 1 - 0 0
Gruppe 2:
9:13 1 - 0 1
3:7 0 - 1 1
8:12:9:13 1 - 0 -
Gruppe 1:
4:12 - 1 0 0
2:3 0 0 1 -
8:9 1 0 0 -
12:14 1 1 - 0
3:7 0 - 1 1
8:12:9:13 1 - 0 -
4:12 - 1 0 0
2 3 4 7 8 9 12 13 14
2:3 * *
8:9 * *
12:14 * *
3:7 * *
8:12:9:13 * * * *
4:12 * *
2 3 4 7 8 9 12 13 14
2:3 * * p
8:9 * *
12:14 * * p
3:7 * * p
8:12:9:13 * * * * p
4:12 * * p
2 3 4 7 8 9 12 13 14
2:3 * * p
12:14 * * p
3:7 * * p
8:12:9:13 * * * * p
4:12 * * p
2:3 0 0 1 -
12:14 1 1 - 0
3:7 0 - 1 1
8:12:9:13 1 - 0 -
4:12 - 1 0 0
y <= (not x3 and not x2 and x1) or
(x3 and x2 and not x0) or
(not x3 and x1 and x0) or
(x3 and not x1) or
(x2 and not x1 and not x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240520 is
port (
x3, x2, x1, x0: in std_logic;
y: std_logic
);
end;
architecture behaviour of quine20240520 is
begin
y <= (not x3 and not x2 and x1) or
(x3 and x2 and not x0) or
(not x3 and x1 and x0) or
(x3 and not x1) or
(x2 and not x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240520testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240520testbench is
component quine20240520
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240520 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
