0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 0
0 0 0 0 0 1
1 0 0 0 1 1
3 0 0 1 1 1
6 0 1 1 0 1
9 1 0 0 1 1
13 1 1 0 1 1
14 1 1 1 0 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
Gruppe 2:
3 0 0 1 1 1
6 0 1 1 0 1
9 1 0 0 1 1
Gruppe 3:
13 1 1 0 1 1
14 1 1 1 0 1
0:1 0 0 0 -
1:3 0 0 - 1
1:9 - 0 0 1
6:14 - 1 1 0
9:13 1 - 0 1
0:1 0 0 0 -
1:3 0 0 - 1
9:13 1 - 0 1
1:9 - 0 0 1
6:14 - 1 1 0
0 1 3 6 9 13 14
0:1 x x
1:3 x x
9:13 x x
1:9 x x
6:14 x x
0 0 0 0 0 1 *
1 0 0 0 1 1 *
2 0 0 1 0 0
3 0 0 1 1 1 *
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1 *
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 1 *
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1 *
14 1 1 1 0 1 *
15 1 1 1 1 0
Richtig
0 1 3 6 9 13 14 prim
0:1 x x x
1:3 x x x
9:13 x x x
1:9 x x
6:14 x x x
0 1 3 6 9 13 14 prim
0:1 x x x
1:3 x x x
9:13 x x x
6:14 x x x
0:1 0 0 0 -
1:3 0 0 - 1
9:13 1 - 0 1
6:14 - 1 1 0
y <= (not x3 and not x2 and not x1) or
(not x3 and not x2 and x0) or
(x3 and not x1 and x0) or
(x2 and x1 and not x0);
Konjunktive Normalform:
y <= (x3 or x2 or x1) and
(x3 or x2 or not x0) and
(not x3 or x1 or not x0) and
(not x2 or not x1 or x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240516 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240516 is
begin
y <= (not x3 and not x2 and not x1) or
(not x3 and not x2 and x0) or
(x3 and not x1 and x0) or
(x2 and x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240516testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240516 is
component quine20240516
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240516 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
