0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
1 0 0 0 1 1
6 0 1 1 0 1
10 1 0 1 0 1
13 1 1 0 1 1
Gruppe 1:
1 0 0 0 1 1
Gruppe 2:
6 0 1 1 0 1
10 1 0 1 0 1
Gruppe 3
13 1 1 0 1 1
1 0 0 0 1 1
6 0 1 1 0 1
10 1 0 1 0 1
13 1 1 0 1 1
y <= (not x3 and not x2 and not x1 and x0) or
(not x3 and x2 and x1 and and not x0) or
(x3 and not x2 and not x1 and not x0) or
(x3 and x2 and not x1 and x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240422 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240422 is
begin
y <= (not x3 and not x2 and not x1 and x0) or
(not x3 and x2 and x1 and and not x0) or
(x3 and not x2 and not x1 and not x0) or
(x3 and x2 and not x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240422testbench is
port (
y: out std_logic
);
end;
architecture behaviour os quine20240422testbench is
component quine20240422
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end compontent;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240422 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
