0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1
0 0 0 0 0 1
1 0 0 0 1 1
4 0 1 0 0 1
6 0 1 1 0 1
7 0 1 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
15 1 1 1 1 1
Gruppe 0:
0 0 0 0 0 1
Gruppe 1:
1 0 0 0 1 1
4 0 1 0 0 1
Gruppe 2:
6 0 1 1 0 1
9 1 0 0 1 1
10 1 0 1 0 1
Gruppe 3:
7 0 1 1 1 1
11 1 0 1 1 1
Gruppe 4:
15 1 1 1 1 1
0:1 0 0 0 -
0:4 0 - 0 0
1:9 - 0 0 1
4:6 0 1 - 0
6:7 0 1 1 -
9:11 1 0 - 1
10:11 1 0 1 -
7:15 - 1 1 1
11:15 1 - 1 1
0:1 0 0 0 -
6:7 0 1 1 -
10:11 1 0 1 -
4:6 0 1 - 0
9:11 1 0 - 1
0:4 0 - 0 0
11:15 1 - 1 1
1:9 - 0 0 1
7:15 - 1 1 1
Gruppe 0:
0:1 0 0 0 -
Gruppe 2:
6:7 0 1 1 -
10:11 1 0 1 -
Gruppe 1:
4:6 0 1 - 0
Gruppe 2:
9:11 1 0 - 1
Gruppe 0:
0:4 0 - 0 0
Gruppe 3:
11:15 1 - 1 1
Gruppe 1:
1:9 - 0 0 1
Gruppe 3:
7:15 - 1 1 1
0:1 0 0 0 -
6:7 0 1 1 -
10:11 1 0 1 -
4:6 0 1 - 0
9:11 1 0 - 1
0:4 0 - 0 0
11:15 1 - 1 1
1:9 - 0 0 1
7:15 - 1 1 1
0 1 4 6 7 9 10 11 15
0:1 * *
6:7 * *
10:11 * *
4:6 * *
9:11 * *
0:4 * *
11:15 * *
1:9 * *
7:15 * *
0 1 4 6 7 9 10 11 15
0:1 * * k
6:7 * * k
10:11 * * k
4:6 * * k
9:11 * * k
0:4 * * k
11:15 * * k
1:9 * * k
7:15 * * k
0 1 4 6 7 9 10 11 15
0:1 * * k
6:7 * * k
10:11 * * k
9:11 * * k
0:4 * * k
11:15 * * k
0:1 0 0 0 -
6:7 0 1 1 -
10:11 1 0 1 -
9:11 1 0 - 1
0:4 0 - 0 0
11:15 1 - 1 1
y <= (not x3 and not x2 and not x1) or
(not x3 and x2 and x1) or
(x3 and not x2 and x1) or
(x3 and not x2 and x0) or
(not x3 and not x1 and not x0) or
(x3 and x1 and x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240420 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecure behaviour of quine20240420 is
begin
y <= (not x3 and not x2 and not x1) or
(not x3 and x2 and x1) or
(x3 and not x2 and x1) or
(x3 and not x2 and x0) or
(not x3 and not x1 and not x0) or
(x3 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240420testbench is
port (
y: out std_logic
);
end;
architecure behaviour of quine20240420 is
component quine20240420
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240420 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
