0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 0
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
5 0 1 0 1 1
8 1 0 0 0 1
11 1 0 1 1 1
14 1 1 1 0 1
Gruppe 1:
1 0 0 0 1 1
2 0 0 1 0 1
4 0 1 0 0 1
8 1 0 0 0 1
Gruppe 2:
5 0 1 0 1 1
Gruppe 3:
11 1 0 1 1 1
14 1 1 1 0 1
1:5 0 - 0 1
4:5 0 1 0 -
2 0 0 1 0
8 1 0 0 0
11 1 0 1 1
14 1 1 1 0
1 2 4 5 8 11 14
1:5 * *
4:5 * *
2 *
8 *
11 *
14 *
1:5 0 - 0 1
4:5 0 1 0 -
2 0 0 1 0
8 1 0 0 0
11 1 0 1 1
14 1 1 1 0
y <= (not x3 and not x1 and x0) or
(not x3 and x2 and not x1) or
(not x3 and not x2 and x1 and not x0) or
(x3 and not x2 and not x1 and not x0) or
(x3 and not x2 and x1 and x0) or
(x3 and x2 and x1 and not x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240419 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240419 is
begin
y <= (not x3 and not x1 and x0) or
(not x3 and x2 and not x1) or
(not x3 and not x2 and x1 and not x0) or
(x3 and not x2 and not x1 and not x0) or
(x3 and not x2 and x1 and x0) or
(x3 and x2 and x1 and not x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240419testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240419testbench is
component quine20240419
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240419 PORT MAP (x3=>x3, x2=>x2, x1=>x1, x0=>x0, y=>y);
