0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
3 0 0 1 1 1
5 0 1 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
14 1 1 1 0 1
15 1 1 1 1 1
Gruppe 2:
3 0 0 1 1 1
5 0 1 0 1 1
10 1 0 1 0 1
Gruppe 3:
11 1 0 1 1 1
14 1 1 1 0 1
Gruppe 4:
15 1 1 1 1 1
3:11 - 0 1 1
5 0 1 0 1
10:11 1 0 1 -
10:14 1 - 1 0
11:15 1 - 1 1
14:15 1 1 1 -
5 0 1 0 1
10:11 1 0 1 -
14:15 1 1 1 -
10:14 1 - 1 0
11:15 1 - 1 1
3:11 - 0 1 1
5 0 1 0 1
Gruppe 2:
10:11 1 0 1 -
Gruppe 3:
14:15 1 1 1 -
Gruppe 2:
10:14 1 - 1 0
Gruppe 3:
11:15 1 - 1 1
3:11 - 0 1 1
5 0 1 0 1
Gruppe 2:
10:11 1 0 1 -
Gruppe 3:
14:15 1 1 1 -
10:11:14:15 1 - 1 -
Gruppe 2:
10:14 1 - 1 0
Gruppe 3:
11:15 1 - 1 1
10:14:11:15 1 - 1 -
3:11 - 0 1 1
5 0 1 0 1
10:11:14:15 1 - 1 -
10:14:11:15 1 - 1 -
3:11 - 0 1 1
5 0 1 0 1
10:11:14:15 1 - 1 -
3:11 - 0 1 1
3 5 10 11 14 15
5 *
10:11:14:15 * * * *
3:11 * *
5 0 1 0 1
10:11:14:15 1 - 1 -
3:11 - 0 1 1
y <= (not x3 and x and not x1 and x0) or
(x3 and x1) or
(not x2 and x1 and x0);
library ieee;
use ieee.std_logic_1164.all;
entity quine20240418 is
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end;
architecture behaviour of quine20240418 is
begin
y <= (not x3 and x and not x1 and x0) or
(x3 and x1) or
(not x2 and x1 and x0);
end;
library ieee;
use ieee.std_logic_1164.all;
entity quine20240418testbench is
port (
y: out std_logic
);
end;
architecture behaviour of quine20240418testbench is
component quine20240418
port (
x3, x2, x1, x0: in std_logic;
y: out std_logic
);
end component;
signal x3, x2, x1, x0: std_logic;
begin
q: quine20240418 PORT MAP (x3=>x3, x=>x2, x1=>x1, x0=>x0, y=>y);
