/media/sda-magnetic/david/Dokumente-15/fernuni-hagen/cs-i-ii/old-cs-2-03/fsm-2021-06-15/2/myadder4.vhdl

-- Also

entity FullAddr2 is
port
(
  a : in bit;
  b : in bit;
  c : in bit;
  s : out bit;
  u : out bit
);
end;

architecture behvr2 of FullAddr2 is
begin
  p1: process (a, b, c)
  begin 
    if (a = b) then
        u <= (a and b) or (b and c) or (a and c);
        s <= a xor b xor c;
    end if;
  end process;
end;