library ieee;
use ieee.std_logic_1164.all;
entity statemachine20240202 is
port (
z3s, z2s, z1s, z0s: out std_logic;
y1, y0: out std_logic;
x: in std_logic;
z3, z2, z1, z0: in std_logic
);
end;
architecture behaviour of statemachine20240202 is
begin
z3s <= (z0);
z2s <= (z2 and x) or (z3 and not x);
z1s <= (z1 and x) or (z2 and not x);
z0s <= (z1 and not x) or (z3 and x);
y1 <= (z0) or (z1 and not x) or (z3);
y0 <= (z0 and x) or (z3 and not x);
end;
library ieee;
use ieee.std_logic_1164.all;
entity statemachine20240202testbench is
port (
z3s, z2s, z1s, z0s: out std_logic;
y1, y0: out std_logic
);
end;
architecture behaviour of statemachine20240202testbench is
component statemachine20240202
port (
z3s, z2s, z1s, z0s: out std_logic;
y1, y0: out std_logic;
x: in std_logic;
z3, z2, z1, z0: in std_logic
);
end component;
signal z3, z2, z1, z0: std_logic;
signal x: std_logic;
begin
fsm1: statemachine20240202 PORT MAP (z3s=>z3s, z2s=>z2s, z1s=>z1s, z0s=>z0s, z3=>z3, z2=>z2, z1=>z1, z0=>z0, y1=>y1, y0=>y0, x=>x);
z0 <= '1' after 0 ns, '0' after 40 ns;
z1 <= '0' after 0 ns, '1' after 40 ns, '0' after 80 ns;
z2 <= '0' after 0 ns, '1' after 80 ns, '0' after 120 ns;
z3 <= '0' after 0 ns, '1' after 120 ns, '0' after 160 ns;
x <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns, '0' after 90 ns, '1' after 100 ns, '1' after 110 ns, '0' after 120 ns, '0' after 130 ns, '1' after 140 ns, '1' after 150 ns, '0' after 160 ns;
end;
