/media/sda-magnetic/david/Dok-15-2023-11-27/informatik/2024-01-01-finite-state-machine/automat2024_01_01.txt

	b a x	b a y
0	0 0 0	1 1 1
1	0 0 1	0 0 1
2	0 1 0	1 0 0
3	0 1 1	1 1 0
4	1 0 0	1 0 0
5	1 0 1	1 1 1
6	1 1 0	1 0 0
7	1 1 1	0 0 1


	b a x	b
0	0 0 0	1
1	0 0 1	0
2	0 1 0	1
3	0 1 1	1
4	1 0 0	1
5	1 0 1	1
6	1 1 0	1
7	1 1 1	0

	b a x	a
0	0 0 0	1
1	0 0 1	0
2	0 1 0	0
3	0 1 1	1
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	0

	b a x	y
0	0 0 0	1
1	0 0 1	1
2	0 1 0	0
3	0 1 1	0
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	1


	b a x	b
0	0 0 0	1
2	0 1 0	1
3	0 1 1	1
4	1 0 0	1
5	1 0 1	1
6	1 1 0	1

	b a x	a
0	0 0 0	1
3	0 1 1	1
5	1 0 1	1

	b a x	y
0	0 0 0	1
1	0 0 1	1
5	1 0 1	1
7	1 1 1	1



	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
6	1 1 0	1

	b a x	a
Gruppe 0:
0	0 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1

	b a x	y
Gruppe 0:
0	0 0 0	1
Gruppe 1:
1	0 0 1	1
Gruppe 2:
5	1 0 1	1
Gruppe 3:
7	1 1 1	1



	b a x	b
Gruppe 0:
0	0 0 0	1
Gruppe 1:
2	0 1 0	1
4	1 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1
6	1 1 0	1

0:2		0 - 0
0:4		- 0 0
2:3		0 1 -
2:6		- 1 0
4:5		1 0 -
4:6		1 - 0


0:2		0 - 0
4:6		1 - 0

0:2:4:6		- - 0

0:4		- 0 0
2:6		- 1 0

0:4:2:6		- - 0

2:3		0 1 -
4:5		1 0 -

	b <= (not x) or (b xor a);





	b a x	a
Gruppe 0:
0	0 0 0	1
Gruppe 2:
3	0 1 1	1
5	1 0 1	1

	a <= (not b and not a and not x) or
			(not b and a and x) or
			(b and not a and x);
	a <= not (
			(b or a or x) and
			(b or not a or not x) and
			(not b or a or not x);
		);

	b a x	y
Gruppe 0:
0	0 0 0	1
Gruppe 1:
1	0 0 1	1
Gruppe 2:
5	1 0 1	1
Gruppe 3:
7	1 1 1	1

0:1		0 0 -
1:5		- 0 1
5:7		1 - 1

		0	1	5	7
0:1		*	*
1:5			*	*
5:7				*	*

		0	1	5	7
0:1		*	*
5:7				*	*

	y <= (not b and not a) or
		(b and x);
	y <= not (
			(b or a) and
			(not b or not x)
		);




	bout <= (not x) or (b xor a);
	aout <= (not b and not a and not x) or
			(not b and a and x) or
			(b and not a and x);
	y <= (not b and not a) or
		(b and x);
library ieee;
use ieee.std_logic_1164.all;

entity meinschaltwerk2024_01_01uebergangsschaltnetz is
port (
	b, a, x: in std_logic;
	bout, aout: out std_logic
);
end;

architecture verhalten of meinschaltwerk2024_01_01uebergangsschaltnetz is
begin
	bout <= (not x) or (b xor a);
	aout <= (not b and not a and not x) or
			(not b and a and x) or
			(b and not a and x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity meinschaltwerk2024_01_01ausgangsschaltnetz is
port (
	b, a, x: in std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinschaltwerk2024_01_01ausgangsschaltnetz is
begin
	y <= (not b and not a) or
		(b and x);

end;

library ieee;
use ieee.std_logic_1164.all;

entity meinschaltwerk2024_01_01testbench is
port (
	bout, aout: out std_logic;
	y: out std_logic
);
end;

architecture verhalten of meinschaltwerk2024_01_01testbench is
	component meinschaltwerk2024_01_01uebergangsschaltnetz
	port (
		b, a, x: in std_logic;
		bout, aout: out std_logic
	);
	end component;
	component meinschaltwerk2024_01_01ausgangsschaltnetz
	port (
		b, a, x: in std_logic;
		y: out std_logic
	);
	end component;
	signal b, a, x: std_logic;
begin
	sn1: meinschaltwerk2024_01_01uebergangsschaltnetz PORT MAP (b=>b, a=>a, x=>x, bout=>bout, aout=>aout);
	sn2: meinschaltwerk2024_01_01ausgangsschaltnetz PORT MAP (b=>b, a=>a, x=>x, y=>y);


	x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	a <= '0' after 0 ns, '0' after 10 ns, '1' after 20 ns, '1' after 30 ns, '0' after 40 ns, '0' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;

	b <= '0' after 0 ns, '0' after 10 ns, '0' after 20 ns, '0' after 30 ns, '1' after 40 ns, '1' after 50 ns, '1' after 60 ns, '1' after 70 ns, '0' after 80 ns;
end;