/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/vhdl/ex01.vhdl

entity multiplexer is 
port 
(
    S:          in bit;
    a, b:       in bit_vector (0 to 3);
    y:          out bit_vector (0 to 3);
);

architecture behaviour of multiplexer is
    signal a, b, y: bit_vector (0 to 3);
begin

end behaviour;