/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-03/fsm-2021-06-15/myadder.vhdl

entity fulladder is
port
(
  a : in bit;
  b : in bit;
  c : in bit;
  u : out bit;
  s : out bit
);
end;
architecture behv of fulladder is
begin 
  s <= a xor b xor c;
  u <= (a and b) or (b and c) or (a and c);
end;