/media/sda-magnetic/david/Dok-15-2023-11-27/fernuni-hagen/cs-i-ii/old-cs-2-01/vhdl-2021-07-16/fulladder/FullAdder.vhdl

entity FullAdder is
port
(
    a: in bit;
    b: in bit;
    cin: in bit;
    s: out bit;
    cout: out bit   
);
end;


architecture structural of FullAdder is
    signal s1, s2, s3, s4, s5: bit;
begin     
    s1 <= a;
    s2 <= b;
    s3 <= cin;
    
    s4 <= s1 xor s2 xor s3;
    s5 <= (s1 and s2) or (s1 and s3) or (s2 and s3);
    
    s <= s4;
    cout <= s5;
end structural;